![]() ![]() 74LVC32 is another low voltage CMOS version of the same. it has lower current consumption and wider voltage range. LS stands for a low power schottky version.Īgain one more type of IC number is also available in the market which is 74HC32 where HC stands for high-speed CMOS version i.e. In TTL logic 2- input OR gate IC number is 74LS32. In TTL logic the internal arrangement differs from that incase of CMOS logics. Thus how the IC looks internally for CMOS. For the third gate pin number 8 and 9 are the inputs whose output is pin number 10 for the last gate pin number 12 and 13 are the inputs whose respective output is at pin number 11. Pin numbers 5 and 6 are inputs for the second gate whose output is pin number 4. Pin 1 and 2 are the input for the first gate and 3 is the respective output for the first gate. Pin number 14 is tvcc where maximum SV DC supply is given which activates the IC. OR Gate IC 4071Ĥ071 is a 14 pin 1C as you can see where four or gates are fixed together having two inputs. An internal gate picture of 4071 can help you understand this IC. 4075 is 3 – input OR gate and 4072 is 4 – input OR gate in CMOS ICs. In digital electronic 4071 is the CMOS IC number of inputs in each gate is two. In CMOS ICs the 4000 series is available. We will now discuss the arrangement of the OR gate on both the ICs. OR gate is available in TTL and CMOS ICS, Where TTL is Transistor – Transistor Logic ICs and CMOS are Complementary MOSFET ICS. Hence entire supply voltage will appear at X and the X becomes at a high logical state or logical 1. So, the base of transistor T 3 will not get sufficient potential to make the transistor T 3 ON. In that case, supply voltage + 5 V will get the path to ground through either of the transistors or both.Īs a result, current starts flowing to the ground from supply through this path, and the entire supply voltage will drop across resistor R. Now, if the base terminal either of the transistors T 1 or T 2 or both are given with + 5 V, the respective transistor as both will be in ON condition. This voltage will appear at node X, and this 0.6 or 0.7 volt is considered as logical 0. In practice, transistor T 3 will not be ideal short circuited it will have some voltage drop across it which will be around 0.6 – 0.7 V. In that condition supply + 5 V will get the path to ground through resistor R′ and transistor T 3.Īs the transistor T 3 is in ON condition it will behave as ideally short circuited, hence the entire supply voltage + 5 V will drop across resistor Rʹ and X terminal (Node) will get 0V. As a result base of the transistor T 3 will get enough potential to make it ON. Now if A and B both are given with 0V, both of the transistors are in OFF condition, hence supply voltage + 5 V will not get the path to the ground through either of the transistors, T 1 and T 2. In this case, the OR gate is referred to as the transistor OR gate. The OR gate can also be realized by using a transistor. Now if both of the inputs A and B are grounded or given 0V, There will be no voltage appears at X and hence X is considered as logical 0. Hence, similarly, 4.4 V will appear at X. Now if both of the inputs are given with +5 V, both diodes will be forward biased. This 4.4 V or 4.3 V is practically considered as logical 1. +5 V means logical 1.Īctually entire 5V will not appear at X, around 0.6 to 0.7 V will drop across the diode as forwarding bios voltage, and the rest of the voltage i.e. When any of the inputs is given with +5V, the respective diode becomes forward biased and behaves as ideally short circuited hence this +5 V will appear at output X. ![]() ![]() ![]() In the above circuit, if A and B are applied with 0V, there will be no voltage appears at X. A simple two inputs OR gate can be realized by using a diode as follows, ![]()
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